This application claims benefit of priority under 35 U.S.C. xc2xa7 119 to Korean Application Serial No. 2001-23181 filed Apr. 28, 2001, the entire contents of which are incorporated by reference herein.
The present invention relates to semiconductor transistors and methods for fabricating the same, more particularly, to high voltage transistors and methods for fabricating the same that improves voltage-resistant characteristics and packing density.
Generally, where an external system which employs a high voltage is controlled by an integrated circuit, the integrated circuit requires a device for controlling the high voltage. The device requires a structure having a high breakdown voltage.
In other words, for a drain or source of a transistor, to which a high voltage is directly applied, the punch-through voltage between the drain, source, and a semiconductor substrate and a breakdown voltage between the drain, source, and a well or substrate should be greater than the high voltage.
A double-diffused metal oxide semiconductor (DMOS) having a PN diode therein is generally used as a semiconductor device for high voltages. In this case, a drain region is formed as a double impurity diffused region so that the punch-through voltage and the breakdown voltage of the transistor become high, while a PN diode is formed between the source and drain, to prevent the device from being broken down by overvoltage when the transistor is turned off.
A known high voltage transistor and a method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating a known high voltage transistor in the art, and FIG. 2 is a sectional view illustrating another known high voltage transistor in the art.
Examples of high voltage transistors include a lateral diffused metal oxide semiconductor (LDMOS) transistor and a double diffused drain (DDD) MOS transistor.
FIG. 1 shows an LDMOS transistor. The LDMOS transistor includes an n-type semiconductor substrate 11, a p-type well 12, a drain region 13, a source region 14, a gate oxide film 15, a gate electrode 16, a drain contact 17, and a source contact 18. P-type well 12 is formed in a predetermined portion of semiconductor substrate 11. Drain region 13 is formed as an n-type heavily doped (n+) impurity layer in one region within p-type well 12 at a predetermined depth. Source region 14 is formed as an n-type heavily doped impurity layer in one region of semiconductor substrate 11 at a predetermined distance from p-type well 12. Gate oxide film 15 is formed, having a first thickness, on drain region 13, p-type well 12, and semiconductor substrate 11 adjacent to p-type well 12. Gate oxide film 15 is also formed, having a second thickness greater than the first thickness, on source region 14 and semiconductor substrate 11 adjacent to source region 14. Gate electrode 16 is formed on a predetermined region of gate oxide film 15 at a predetermined distance from source region 14, overlapping drain region 13 and p-type well 12 adjacent to drain region 13 at an upper portion. Drain contact 17 and source contact 18 are in respective contact with drain region 13 and source region 14 through gate oxide film 15.
FIG. 2 shows a high voltage transistor having a DDD structure. The high voltage transistor having a DDD structure includes a p-type substrate 21, a gate oxide film 25, a gate electrode 26, an n-type drift region 22, an n-type heavily doped drain region 23, an n-type heavily doped source region 24, a drain contact 27, and a source contact 28. Gate oxide film 25 is formed on p-type substrate 21. Gate electrode 26 is formed in a predetermined portion on gate oxide film 25. N-type drift region 22 is formed in semiconductor substrate 21 at both sides below the gate electrode 26 at a predetermined depth, partially overlapping gate electrode 26 at a lower edge of gate electrode 26. N-type heavily doped drain region 23 is formed within drift region 22 at one side of gate electrode 26. N-type heavily doped source region 24 is formed within drift region 22 at the other side of gate electrode 26. Drain contact 27 and source contact 28 are in respective contact with drain region 23 and source region 24 through gate oxide film 25.
In known high voltage transistors, to improve voltage-resistant characteristics, the distance between the edge portion of the gate electrode and the heavily doped source and drain regions, i.e., the traverse length of the drift region is increased. The increased length of the drift region increases the size of the high voltage transistor and, as a consequence, this reduces packing density.
Accordingly, the present invention is directed to high voltage transistors and methods for fabricating the same. The present invention provides a high voltage transistor and a method for fabricating the same that improves voltage-resistant characteristics and reduces a size of a device to improve packing density.
In accordance with the invention, a high voltage transistor includes a semiconductor substrate having a first region and second and third regions, the second and third regions neighboring to the first region with boundaries, first and second drift regions respectively formed in the second and third regions at a first depth, insulating films formed at a second depth less than the first depth, having a predetermined width respectively based on the boundary between the first and second regions and the boundary between the first and third regions, a channel ion injection region formed with a variable depth along a surface of the semiconductor substrate belonging to the first region and the insulating films, a gate insulating film formed on the channel ion injection region, partially overlapping the insulating films at both sides around the channel ion injection region, source and drain regions formed within the first and second drift regions, and a gate electrode formed to surround the gate insulating film and to partially overlap the insulating films.
In another aspect of the present invention, a method for fabricating a high voltage transistor includes the steps of forming first and second drift regions in a predetermined region of a semiconductor substrate, forming drain and source regions within the first and second drift regions, respectively forming trenches, having a predetermined width, in the first and second regions around a boundary between the first and second drift regions and the semiconductor substrate between the source and drain regions, exposing the semiconductor substrate, forming a channel region within a surface of the exposed semiconductor substrate, burying an insulating film in the trenches, forming a gate insulating film on the semiconductor substrate including the channel region and on the insulating film at both sides of the semiconductor substrate, and forming a gate electrode at an upper portion and both sides of the gate insulating film.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.